In high speed communication channels the channel distorts transmitted pulses which in turn causes such problems as timing jitter and intersymbol interference. By predistorting a pulse, before it is acted upon by the channel, the channel effects can be compensated. Prior art techniques for equalization of binary data communication channels have employed some form of the nonrecursive or transversal filter, a digital implementation of which is shown in FIG. 1. This equalizer has N multipliers 12, N-1 storage registers 14, an N input summer 16, and a analog to digital (A/D) converter 18. The multiplier coefficients a.sub.0, a.sub.1, . . . , a.sub.N-1 which determine the characteristics of the equalizer and therefore of the equalized channel, can be specified by any of a number of well established techniques.
Typical multiplier coefficient development is taught in the prior art references of "Principles of Data Communication" by R. W. Lucky, J. Salz, and E. J. Weldon, Jr., McGraw-Hill, Book Company 1968; pages 130-136 and "Applications of Linear Programming to the Time-Domain Design of Digital-Filter Equalizers" by D. W. Burlage and R. C. Houts, IEEE Transactions on Communications, Volume COM-21, No. 12, December 1973. Some techniques are adaptive in that the equalizer continues to adjust the multiplier coefficients during transmission of binary data to null some error criterion. Similar to the Burlage et al. article published by IEEE, a technical report by R. C. Houts and D. W. Burlage discloses substantially identical teachings but provides additional detail, as for example, typical programming fundamentals and subroutines useful in the design of digital filters. The technical report is "The Use of Linear Programming Techniques to Design Optimal Digital Filters for Pulse Shaping and Channel Equalization" published in April, 1972 as Technical Report Number 142-102 by the Communication System Group, Bureau of Engineering Research, University of Alabama.
The conventional preset equalizer of FIG. 1 is normally placed at the channel output with A/D converter 18 sampling at a rate of 1/T, which is referred to as the baud rate, and converting the analog sample to a C-bit digital word, C being the number of bits in each word of the equalizer. In conventional equalizers the baud rate typically equals the transmission rate 1/T.sub.b of binary data over the channel. However, it has been shown by Houts et al (for example pages 68-81 of Chapter 4) that an improved equalizer takes B samples of the channel output for every binary data interval with B typically ranging from 2 to 5. Consequently, B represents the ratio of A/D converter sampling rate to the binary data rate, i.e., B=T.sub.b /T and the storage registers 14 of FIG. 1 span M=N/B binary data intervals, where N is the length of a conventional equalizer.
Since the equalizer is a linear system, the placement of the equalizer at the transmitter or receiver is immaterial from a theoretical viewpoint. However, as is made apparent hereinbelow, a considerable savings in hardware circuitry can result from placing the equalizer at the channel input and taking advantage of the binary nature of the data source.